1. Field of the Invention
The present invention relates to apparatuses for receiving television and radio broadcasting, especially digital broadcasting.
2. Description of the Background Art
Shown in FIG. 14 is the structure of an automatic gain control apparatus (hereinafter referred to as AGC apparatus) conventionally used for a digital broadcast receiving apparatus. The AGC apparatus AGC includes a tuner 30, an A/D converter 6, a level detector LD, and an automatic gain control signal generator (hereinafter, AGC signal generator) SG. The tuner 30 includes an RF automatic gain controller 2 for controlling the gain of a digital broadcast wave RF, a mixer 3, an oscillator 4, an IF automatic gain controller 5 for controlling the gain of an intermediate frequency signal Sif, and an RF gain control point setter 40.
In the tuner 30, the RF automatic gain controller 2 carries out automatic gain control and amplification of the digital broadcast wave RF for generating a digital broadcast wave Srf. This amplification is carried out based on an RF automatic gain control signal (hereinafter, RF AGC signal) SAGr supplied by the RF gain control point setter 40. The mixer 3 frequency-converts the digital broadcast wave Srf for generating the intermediate frequency signal Sif. This frequency conversion is carried out based on a reference frequency signal SB supplied by the oscillator 4. The IF automatic gain controller 5 carries out automatic gain control and amplification of the intermediate frequency signal (hereinafter, IF signal) Sif for generating a modulated analog signal SMA. In short, the tuner 30 generates the modulated analog signal SMA by frequency-converting and amplifying the digital broadcast wave RF received via an antenna.
The A/D converter 6 converts the modulated analog signal SMA from analog to digital for generating a modulated digital signal SMD. The modulated digital signal SMD is outputted to the following demodulation processing and also to the level detector LD.
The level detector LD detects the average level of the modulated digital signal SMD, and generates a level signal SL. The level signal SL indicates the level of the output from the IF automatic gain controller 5, that is, the level of the modulated analog signal SMA.
The AGC signal generator SG generates an automatic gain control signal (hereinafter, AGC signal) SAG based on the level signal SL. The AGC signal SAG is a control signal for controlling the gain of the RF automatic gain controller 2 and the IF automatic gain controller 5.
The RF gain control point setter 40 generates, based on the AGC signal SAG, an IF automatic gain control signal (hereinafter, IF AGC signal) SAGi for controlling the IF automatic gain controller 5 and an RF automatic gain control signal (hereinafter, RF AGC signal) SAGr for controlling the RF automatic gain controller 2.
Shown in FIG. 15 is the structure of the level detector LD in detail. The level detector LD includes a subtractor 12, an adder 13, a delay unit 14, and a bit shifter 15 (represented as “2−n” in FIG. 15). Note that n represents the number of shift bits. The adder 13 and the delay unit 14 form an integrator 100. For example, if an average value is obtained from 128=27 values of data, n is set to 7. If obtained from 2048=212 data values, n is set to 12.
The digital modulated signal SMD coming from the A/D converter 6 goes to the subtractor 12, where an averaged signal Y/2″received from the bit shifter 15 is subtracted from the modulated digital signal SMD. Then, the subtraction result is outputted to the integrator 100.
Shown in FIG. 16 is the structure of the AGC signal generator SG in detail. The AGC signal generator SG includes a subtractor 16, a reference value provider 17, a multiplier 18, a constant provider 19, an integrator 22, a level converter LC, a PWM (Pulse Width Modulator) 42, and a low-pass filter 43. The integrator 22 includes an adder 20 and a delay unit 21. The level converter LC includes a multiplier 23, an inverse coefficient provider 24, an adder 38, and a compensation coefficient provider 39.
The subtractor 16 finds an error between the level signal SL supplied by the level detector LD and a predetermined reference value R supplied by the reference value provider 16, and generates an error signal SE. Note that, for the purpose of simplifying the description, signals and parameters may hereinafter be simply represented by reference characters as required. The multiplier 18 multiplies the error signal SE received from the subtractor 16 by a constant G received from the constant provider 19 to generate G·SE for output to the integrator 22.
In the integrator 22, the delay unit 21 first delays G·SE outputted from the multiplier 18 by a control cycle t, and then the adder 19 adds the delayed signal to a current output from the multiplier 18 for integration of G·SE. The integration result is outputted as an integrated signal Z from the delay unit 21 to the adder 20 and the level converter LC. Note herein that one control cycle is a sequence of control processing successively carried out in the conventional automatic gain controller or the automatic gain controller according to the present invention, and their components. Also note that one control cycle period is a time period required for execution of one control cycle, that is, a period from start of one control cycle until before start of the next control cycle.
In the level converter LC, the multiplier 23 multiplies the integrated signal Z outputted from the integrator 22 by “−1” outputted from the inverse coefficient provider 24 to invert the polarity of the integrated signal Z, and generates −Z. The adder 38 adds a compensation coefficient OB provided by the compensation coefficient provider 39 to −Z provided by the multiplier 23, and generates −Z+OB. The PWM 42 modulates the pulse width of −Z+OB received from the adder 38 to generate a square-wave signal Sr. The low-pass filter 43 extracts low-frequency components from the square-wave signal Sr supplied by the PWM 22 to generate the AGC signal SAG having a predetermined control voltage. Consequently, the gain of a loop formed by the tuner 30, the level detector LD, and the AGC signal generator SG is adjusted.
The level converter LC is briefly described below. The level converter LC is provided to normalize the value of the integrated signal Z outputted from the integrator 22 before processed by the PWM 42 for correct gain control. Therefore, the inverse coefficient provider 24 provides the inverse coefficient, that is, a predetermined negative value, to the multiplier 23 for inverting the polarity of the integrated signal Z. The compensation coefficient provider 39 provides, for the sake of convenience of the processing in the PWM 42, the compensation coefficient OB having a predetermined value for compensating the inverted integrated signal Z (−Z) so that it takes a positive value or 0.
The value of the compensation coefficient OB is determined based on the inverse coefficient provided by the inverse coefficient provider 24 and the number of output bits of the integrator 22. Now, consider the case where the inverse coefficient is −1, and the number of output bits of the integrator 22 is 12. In this case, the integrated signal Z takes a value in the range of −2048 to +2047. If the compensation coefficient OB is set to 12 bits (OB=2048), which is the number of output bits of the integrator 22, the value of −Z+OB outputted from the adder 38 falls within the range of 0 to +4095.
If the error signal SE indicates 0, the value of −Z+OB outputted from the adder 38 falls within the range of +2048 (OB). If the error signal SE has a negative value, −Z+OB falls within the range of 0 to +2047. As such, correct gain control can be achieved according to the average level of the digital broadcast wave Srf.
In other words, when a predetermined time has passed and the outputs from the integrator 22 become converged, the signal indicating any one of the following three values is supplied to the PWM 42, where the number of output bits of the integrator 22 is 12.
Firstly, the output from the integrator 22 has a positive value if the average level of the digital broadcast wave RF is higher than the reference value R set in the reference value provider 17. Therefore, the PWM 42 receives a value of less than 2048.
Secondly, the PWM 42 receives a value of 2048 if the average level of the digital broadcast wave RF is equal to the reference value R.
Thirdly, the PWM 42 receives a value of equal to or larger than 2049 if the average level of the digital broadcast wave RF is lower than the reference value R.
Shown in FIG. 17 are waveforms of the square-wave signal Sr. In the PWM 42, the pulse width of the square-wave signal Sr is changed according to the received −Z+OB. For example, if −Z+OB is 4095, the square-wave signal Sr constant at 1 is outputted, as represented by a waveform W1. If −Z+OB is 2048, the square-wave signal Sr alternately indicating 0 and 1 is outputted, as shown in FIG. 17, as represented by a waveform W2. If −Z+OB is 0, the square-wave signal Sr constant at 0 is outputted, as represented by a waveform W3.
Then, the square-wave signal Sr is converted by the low-pass filter 43 into the AGC signal SAG having a DC voltage. Then, the AGC signal SAG is outputted to the RF gain control point setter 40.
The RF gain control point setter 40 generates the RF AGC signal SAGr for attenuating the gain of the RF automatic gain controller 2 when the value of the AGC signal SAG becomes lower than a predetermined value. The RF gain control point setter 40 also generates the IF AGC signal SAGi for always varying the gain of the IF automatic gain controller 5.
FIGS. 15 and 16 schematically illustrate processes on various signals generated in the level detector LD and the AGC signal generator SG in an arbitrary control cycle t. Throughout this specification, the control cycle is represented as t. That is, a control cycle previous to the control cycle t is represented as t with a natural number added thereto, and the one next thereto as t with a natural number subtracted therefrom. As such, the control cycle t is also a parameter indicating a relative time. Furthermore, for the sake of convenience, the control cycle t may be simply referred to as “t”, and also each signal and parameter may be referred to as its reference character.
As shown in FIG. 15, the subtractor 12 of the level detector LD subtracts the averaged signal Y(t+1)/2n supplied by the bit shifter 15 from SMD(t) supplied by the A/D converter 6 to generate SMD(t)−Y(t+1)/2n.
The adder 13 of the integrator 100 adds SMD(t)−Y(t+1)/2n supplied by the subtractor 12 to the integrated signal Y(t+1) supplied by the delay unit 14 to generate SMD(t)−Y(t+1)/2n+Y(t+1)=SMD(t)+Y(t+1)(1−2−n).
The delay unit 14 delays SMD(t)+Y(t+1)(1−2−n) outputted from the adder 13 by one control cycle t to generate an integrated signal Y(t+1).
The bit shifter 15 shifts the integrated signal Y(t+1) by the predetermined number of shift bits n to generate an averaged signal Y(t+1)/2n. This averaged signal Y(t+1)/2n is equivalent to the average of 2n data values of the modulated digital signal SMD supplied to the level detector LD. In this sense, the number of shift bits n defines the number of data values required for finding the average value by the bit shifter 15. In other words, 2n is the number of data values required for finding the average value of the modulated digital signal SMD supplied to the level detector LD, and the number of shift bits n is an averaging coefficient. Hereinafter, 2n is referred to as the number of data values for averaging.
Next, as shown in FIG. 16, the subtractor 16 of the AGC signal generator SG subtracts the reference value R provided by the reference value provider 17 from the level signal SL supplied by the level detector LD to generate the error signal SE(t).
The multiplier 18 multiplies SE (t) supplied by the subtractor 16 by the constant G provided by the constant provider 19 to generate G·SE(t).
The adder 20 of the integrator 22 adds G·SE(t) supplied by the multiplier 18 to the integrated signal Z(t+1) outputted from the delay unit 21 to generate G·SE (t)+Z (t+1).
The delay unit 21 delays G·SE(t)+Z(t+1) supplied by the adder 20 by one control cycle t to generate the integrated signal Z(t+1).
The multiplier 23 of the level converter LC multiplies the integrated signal Z(t+1) received from the delay unit 21 by the inverse coefficient “−1” received from the inverse coefficient provider 24 to generate −Z(t+1).
The adder 38 adds −Z(t+1) supplied by the multiplier 23 to the compensation coefficient OB provided by the compensation coefficient provider 39 to generate −Z(t+1)+OB.
The PWM 42 modulates the pulse width of −Z(t+1)+OB supplied by the level converter LC to generate a square-wave signal Sr. The low-pass filter 23 extracts low-frequency components from the square-wave signal Sr supplied by the PWM 42 to generate the AGC signal SAG at a desired stable level.
Shown in FIG. 18 are changes in the gain of the RF automatic gain controller 2 and the IF automatic gain controller 5 with respect to the digital broadcast wave RF. In FIG. 18, the vertical axis VA represents attenuation (dB) from the maximum gain, and the lateral axis LRF represents the level of the digital broadcast wave RF. A solid line LR represents gain attenuation of the RF automatic gain controller 2, while a dotted line LI represents that of the IF automatic gain controller 5.
As is evident from FIG. 18, when the attenuation is 0, the maximum gain is observed for both of the RF and IF automatic gain controllers 2 and 5. Between −78 dBm and −5 dBm, the gain is attenuated mainly by the RF automatic gain controller 2, but also slightly by the IF automatic gain controller 5. This is because the ratio of the RF AGC signal to attenuation achieved by the RF automatic gain controller 2 is larger than the ratio of IF AGC signal to attenuation achieved by the IF automatic gain controller 5.
When the level of the digital broadcast wave RF is in the ranges of 0 dBM to −178 dBm and over −5 dBm, the gain is attenuated only by the IF automatic gain controller 5.
Under −78 dBm, the RF automatic gain controller 2 generates the RF AGC signal SAGr to prevent attenuation in itself. Over −5 dBm, the RF automatic gain controller 2 can hardly attenuate the gain, and the IF automatic gain controller 5 automatically controls the gain.
The reason of such control is that the gain of the RF and IF automatic gain controllers 2 and 5 has to be appropriately adjusted according to the level of the digital broadcast wave RF. More specifically, in a low electric field intensity where the digital broadcast wave RF is under −78 dBm, degradation of the C/N (Carrier to Noise) ratio at the tuner 30 has to be prevented. In that case, control is carried out so that the noise factor at the tuner 30 becomes lower, that is, the gain of the RF automatic gain controller 2 becomes maximum.
As the level of the digital broadcast wave RF becomes higher, the capabilities at the mixer 3 of suppressing intermodulation-distortion interference and adjacent-channel interference have to be increased. Therefore, over −78 dBm, the gain of the RF automatic gain controller 2 is mainly attenuated so that the level of the signal supplied to the mixer 3 does not become increased. Then, over −5 dBm where the RF automatic gain controller 2 can no longer control the gain, the IF automatic gain controller 5 is started in operation.
Shown in FIG. 19 are changes in the gain of the RF automatic gain controller 2 and the IF automatic gain controller 5 with respect to the level of the digital broadcast wave RF in an AGC apparatuses disclosed in Japanese Patent Gazettes Nos. 2699698 and 2778260. Also in FIG. 19, the vertical axis VA represents attenuation (dB) from the maximum gain, and the lateral axis LRF represents the level of the digital broadcast wave RF. A solid line LR represents gain attenuation of the RF automatic gain controller 2, while a dotted line LI represents that of the IF automatic gain controller 5.
In these automatic gain controllers for increasing the capabilities of suppressing intermodulation-distortion interference and adjacent-channel when the level of the digital broadcast wave RF is −78 dBm, the gain of the RF automatic gain controller (corresponding to a low-noise amplifier in the above Gazette No. 2699698 and a first gain control circuit in the above Gazette No. 2778260) is maximized, while the gain of the IF automatic gain controller is attenuated. Over −78 dBm, the gain of the IF automatic gain controller is made constant, while the gain of the RF automatic gain controller is attenuated. Consequently, the maximum attenuation is 65 dB for the RF automatic gain controller, and 17 dB for the IF automatic gain controller. Therefore, the amount of change in gain, that is, a dynamic range, of the receiver is 82 dB.
However, the receive level of the digital broadcast wave for ground-wave digital broadcast receivers to display on television is −85 dBm to 5 dBm, and the dynamic range is 90 dB. Controlling the level of the RF input signal by both RF and IF automatic gain controllers requires some margin in dynamic range, and therefore the dynamic range has to be 100 dB in reality. Also, for ensuring the dynamic range of 100 dB, the maximum attenuation of the IF automatic gain controller may be controlled to 35 dB, as shown in FIG. 20.
In this case, however, when the level of the digital broadcast wave RF is under −60 dBm, the gain of the RF automatic gain controller is maximized, while the gain of the IF automatic gain controller is attenuated. Over −60 dBm, the former is attenuated, while the latter is made constant. Consequently, the attenuation of the RF automatic gain controller 2 at −50 dBm is 13 dB, thereby increasing the level of the signal supplied to the mixer 3. Therefore, when the level of the digital broadcast wave is at −50 dBm, for example, the capability of suppressing intermodulation-distortion interference is significantly degraded and, in turn, the capability of suppressing adjacent-channel interference is also significantly degraded.
As stated above, in the conventional AGC apparatus AGC characterized by the changes in the gain of RF and IF automatic gain controller 2 and 5 as shown in FIG. 18, when the digital broadcast wave RF is in the range of −78 dBm to 15 dBm, the gain of the RF automatic gain controller 2 is attenuated. In that range, the gain of the IF automatic gain controller 5 is also attenuated, although slightly, by approximately 7 dB (changed from 18 dB to 25 dB).
For example, the gain attenuation of the IF automatic gain controller 5 is 18 dB when the level of the digital broadcast wave RF is at −78 dBm, while 22 dB at −50 dBm. As a result, the attenuation is increased by 4 dB. Therefore, the signal supplied to the mixer 3 is increased in level by 4 dB at −50 dBm, compared with the case where the gain attenuation of the IF automatic gain controller 5 does not change at all in the range of −78 dBm to −5 dBm. Such increase disadvantageously causes degradation by 4 dB in the capability of suppressing intermodulation-distortion interference and, in turn, the capability of suppressing adjacent-channel interference.
In another example, the gain attenuation of the IF automatic gain controller 5 is 18 dB when the level of the digital broadcast wave RF is at −78 dBm, while 25 dB at −5 dBm. As a result, the attenuation is increased by 7 dB. Therefore, the signal supplied to the mixer 3 is increased in level by 7 dB at −5 dBm, compared with the case where the gain attenuation of the IF automatic gain controller 5 does not change at all in the range of −78 dBm to −5 dBm. Such increase disadvantageously causes degradation by 7 dB in capability of suppressing intermodulation-distortion interference.
Furthermore, in the above Gazettes, when ground-wave digital broadcasting is received, the stronger the capability of suppressing adjacent-channel interference is made, the narrower the dynamic range becomes. And, the wider the dynamic range is made, the weaker the capability of suppressing intermodulation-distortion interference becomes, resulting in significant degradation of the capability of suppressing the adjacent-channel interference.